PADI2-3, the second iteration of FEE for CBM Time-of-Flight Measurements

From the in-beam tests of the PADI1 prototype [1] we have recognized that the minimization of the crosstalk between channels has a priority for further developments. In the upcoming design we have changed the biasing type from voltage biasing to current biasing. The bias block used in PADI2-3 ASIC is a constant-transconductance bias circuit having a wide swing cascode current mirrors similar to the one described in [2]. It gives two currents for each channel and at the channel level all needed biasing voltages are created locally. For the bias block we have used a special layout routing technique in order to realize a good matching of the eight output currents. The layout was designed in a few successive optimization steps involving the simulation with parasitic elements extracted. Finally the eight currents are in a few percent close to the medium value. According to simulations, the increase of CTRR at chip level relative to PADI1 will be of minimum 20 dB. We